1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof; in particular, to a semiconductor device having metal silicide layers on a source region and a drain region, and a manufacturing method thereof.
2. Description of the Related Art
As higher integration and further miniaturization of a semiconductor device such as a thin film transistor (also referred to as a TFT) are achieved, lower contact resistance with a doped region (e.g., a source region or a drain region of a transistor) formed in a semiconductor film including silicon, and lower resistance of the doped region have been required. It is effective in lowering the resistance to form a metal silicide layer such as a titanium silicide layer, a cobalt silicide layer, or a nickel silicide layer on a surface of the semiconductor film. Reduction in the resistance of the doped region and in the contact resistance therewith leads to reduction in heat generation and power consumption of a transistor.
Such a metal silicide layer can be formed in the following manner: a metal film is formed over a transistor so as to be in contact with a doped region formed in a semiconductor film including silicon, and then heat treatment or the like is carried out to the metal film and the semiconductor film, so that the silicon is diffused into the metal film or the metal is diffused into the semiconductor film including silicon; thus, the metal and the silicon react with each other (see Reference 1: Japanese Translation of PCT International Application No. 2003-526198; Reference 2: Japanese Published Patent Application No. H8-70053; and Reference 3: Japanese Published Patent Application No. 2006-74071).
In such a transistor having a metal silicide layer, however, the metal silicide can undesirably enter a channel formation region to cause a malfunction of the transistor. In particular, when a semiconductor film is thin, it is difficult to control the thickness of the metal silicide layer. In forming a metal silicide layer, the thermal treatment temperature, the thermal treatment time, and the thickness of the metal film are controlled; however, since it is difficult to control the thermal treatment, a method can be given in which the entire metal film which has been formed with the thickness controlled reacts with silicon in the semiconductor film. In such a method, when the semiconductor film is thin, the metal film also needs to be thinned (e.g., to a thickness of less than 10 nm) accordingly; however, it is difficult to form a thin metal film having a thickness of less than 10 nm, with the thickness controlled in nanometers. As an example of a technique for preventing metal silicide from entering a channel formation region, Reference 1 proposes that by ion implantation of silicon into a part of source/drain regions, a crystalline state is changed to an amorphous state to form an amorphous silicon layer, and only the amorphous silicon layer selectively reacts with the metal to form silicide. However, such a change of the part of the source/drain region to amorphous silicon complicates a process and increases manufacturing cost.
Further, Reference 4 (Japanese Patent No. 3658664) discloses that a gate electrode is formed over a substrate; a semiconductor film formed of amorphous or polycrystalline silicon and a silicide film are formed thereover and then are patterned by etching; and source/drain regions are formed, so that a thin film transistor is manufactured. In the manufacturing method disclosed in Reference 4, specifically, an n+-Si film is formed over a semiconductor film that is formed over a gate electrode with a silicon nitride film interposed therebetween; a thin oxide film is formed on a surface of the n+-Si film; and a metal film is formed on the thin oxide film to form a metal silicide layer between the metal film and the n+-Si film. By forming the thin oxide film on the surface of the n+-Si film in such a manner, the thickness of the metal silicide layer formed between the n+-Si film and the metal film can be minimized, which facilitates etching of the metal silicide layer. In such a manufacturing method of a thin film transistor, however, the gate electrode needs to withstand a high temperature or the like in forming the semiconductor film because the source and drain regions (the semiconductor film) are formed over the gate electrode after forming the gate electrode; therefore, there are limitations on the material or thickness of the gate electrode. In particular, when a polycrystalline silicon film is formed as the semiconductor film, a method can be given in which an amorphous silicon film is annealed with laser to form polycrystalline silicon; however, in a bottom gate structure, it is difficult to carry out laser annealing because of limitations such as heat resistance or thermal conductivity of the gate electrode. Further, a bottom gate structure cannot be formed on an SOI (silicon on insulator) substrate in which a single crystalline silicon layer is formed on an insulator using an SOI technique such as the Smart Cut method. In the manufacturing method of a thin film transistor which is described in Reference 4, the silicon nitride film that functions as a channel etch stopper in patterning the metal silicide layer, the n+-Si film, and the semiconductor film is formed in a pattern over a portion of the semiconductor film which functions as a channel formation region over the gate electrode.
In a thin film transistor, it is known that the subthreshold swing, which shows switching characteristics (subthreshold characteristics) of a transistor, can be improved by thinning a channel formation region. The subthreshold swing is a gate voltage which is necessary for increasing a current (subthreshold current) between a source electrode and a drain electrode by one order of magnitude. As the subthreshold swing becomes smaller, the inclination of a subthreshold current with respect to a gate voltage becomes greater; in other words, the switching characteristics become better. Using a TFT with a small subthreshold swing has advantages such as suppression of power consumption which is due to reduction in operation voltage and reduction in off leakage current. However, when an entire semiconductor film in which a channel formation region is formed is thinned in order to thin the channel formation region, a source region and a drain region are also thinned; thus, there arise problems of increase in sheet resistance in the source and drain regions and increase in contact resistance between the source and drain regions and source and drain electrodes. Therefore, it is preferable that the thickness of the channel formation region be reduced while an adequate thickness of the source and drain regions is secured.
Reference 5 (Japanese Published Patent Application No. 2004-281687) discloses an example of such a technique for thinning a channel formation region. According to Reference 5, a photosensitive resist formed over a semiconductor layer (operation layer) is exposed to light using a half-tone mask, thereby making the thickness of a part of the photosensitive resist over a channel formation region in a TFT formation region smaller than the thickness of a part of the photosensitive resist in a region other than the channel formation region. Then, the photosensitive resist is further processed to remove the part of the photosensitive resist over the channel formation region, and the remaining part of the photosensitive resist is used as a mask to thin the channel formation region by wet-etching or dry-etching. However, no mention is made of forming a metal silicide layer in Reference 5.